
¡¾ÅäÖüò½é¡¿
1¡¢FPGAоƬ£ºEP1C6Q240C8£¬Çëµã»÷ ²ì¿´CycloneϵÁнéÉÜ£»
2¡¢DRAMоƬ£ºhynix57V641620 (Ϊ64M bits = 8M Bytes)£»
3¡¢FlashоƬ£ºAMD29LV160,16M bits = 2M
Bytes£¨Àϰ汾ûÓУ¬Ð°汾Ôö¼ÓÁË£¬¼Û¸ñ²»±ä£©£»
4¡¢ÅäÖÃоƬ£ºEPCS1(1Mbits)
5¡¢SRAM£ºIS61LV25616£¬256¡Á16 bits £½ 512K
Bytes£»
6¡¢¹©µçµç·£ºAS1084-3V3£¨3A¡¢3.3VÊä³öµÍѹ²îÎÈѹ¼¯³Éµç·£©+ AS1084T(3A¿Éµ÷µÍѹ²îÎÈѹ¼¯³Éµç·£©,¿ÉÒÔͨ¹ýUSB¿ÚÈ¡µç£¬»òÕß5VµçÀÂÈ¡µç¡£
7¡¢Ê±Öӵ緣º50MÓÐÔ´¾§Õñ£»
8¡¢RS232½Ó¿Úµç·£º²ÉÓÃmax3232,Ö§³Ö1·RS232ͨѶ½Ó¿Ú£»
9¡¢CH341
USB¿ÚͨѶµç·£¬ÊʺϱʼDZ¾Óû§£»
10¡¢6¸ö¶ÀÁ¢°´¼ü£»
11¡¢7¸öָʾµÆ£»
12¡¢Òý³öFPGAÏÂÔØ½Ó¿Ú£»
13¡¢Òý³öIOÊýÄ¿£º54¸ö¡£ÕâЩÒý½ÅÒѾͨ¹ýËÄÅÅ40Pin²åÕëÒý³ö¡££¨×¢£ºÕâЩÒý½Å»ù±¾Îª¹²ÓÃÒý½Å£¬ÄúÔÚʹÓÃʱºòÐèҪעÒ⣬±ÜÃâ³åÍ»¡£±ÈÈ磬´ó¶àÊýÒý½ÅÒѾͬʱ½Óµ½FlashоƬÉÏ£¬Èç¹ûÄúµÄ¿ª·¢°åÉÏÓÐFlash,ÄúÐèÒªÓëFlash·Öʱ¸´ÓÃÕâЩÒý½Å¡££©
14¡¢µç·°å²ÄÁÏÓ뺸½Ó¹¤ÒÕ£º²ÉÓÃ Ë«Ãæ°åÖÆ×÷ + רҵÁ÷Ë®ÏßÉÏ»ØÁ÷º¸½Ó¹¤ÒÕ ¡£
¡¾EP1C6ƬÄÚ×ÊÔ´¼òÃ÷ÁÐ±í¡¿
1.Âß¼µ¥Ôª£º¹²5980¸ö£¬Ö§³Ö½Ó½ü12ÍòÃŵÄÉè¼Æ£»
2.ÄÚǶRAM£º¹²92£¬160bits £»
3.°üº¬2¸öPLL £»
4.°üº¬34¸ö²î·ÖͨµÀ£»
5.×î´óÓû§I/OÊý£º185
¡¾¹¦ÄÜÓëÓÃ;¡¿
1¡¢Ñ¸ËÙÑéÖ¤Äú×Ô¼ºµÄÉè¼ÆÓëÏë·¨¡£EP1C6°üº¬Âß¼µ¥Ôª5980¸ö£¬Ö§³Ö½Ó½ü12ÍòÃŵÄÉè¼Æ£¬×ã¹»ÑéÖ¤Ò»°ã¹æÄ£µÄÉè¼Æ¡£Ðí¶àCPLD¿ª·¢°åÒòΪÈÝÁ¿Ì«Ð¡£¬ÎÞ·¨ÑéÖ¤µÄÉè¼Æ£¬±¾¿ª·¢°å¶¼¿ÉÒÔÇá¶øÒ×¾ÙµÃÍê³É¡£
2¡¢Ñ¸ËÙÈëÃÅnios´¦ÀíÆ÷¡£ezNiosC6ϵÁÐÊÇĿǰ¼Û¸ñ×îµÍµÄÁ¼ºÃÖ§³ÖniosÈíºË´¦ÀíÆ÷µÄ¿ª·¢°å¡£(ezNios660°üº¬64Mbits
DRAM),×ã¹»ÔËÐдó¶àÊýµÄ³ÌÐò¡££¨Ê¹ÓÃʱºò£¬¿ÉÒÔ½«Program memory¡¢Read-only data
memory¡¢Read/Write data
memory¾ùÉèΪsdram£¬³ÌÐòÓëÊý¾Ýͨ¹ýJTAG½Ó¿Ú´«Ë͵½sdramÖУ¬²¢²»ÐèÒªflash£¬¾Í¿ÉÒÔÔËÐдó¶àÊýµÃ³ÌÐò£©¡£
3¡¢½ÌѧÓëѧϰ¡£ÊǽÌѧ»òÕßѧϰÊý×ֵ緡¢Verilog£¨»òÕßVHDL)Ó²¼þÃèÊöÓïÑԵĵÃÁ¦ÖúÊÖ¡£³£ÓõÄCPLD¿ª·¢°åÒòΪÈÝÁ¿Ì«Ð¡£¬ÉÔ΢¸´ÔÓÒ»µãµÄ
Éè¼Æ£¬¾ÍÈÝÄɲ»Ï£¬Ó°ÏìÁËÄúµÄѧϰ£»±¾¿ª·¢°å°üº¬Âß¼µ¥Ôª5980¸ö£¬ÄÚǶRAM¹²92£¬160bits£¬Ö§³Ö½Ó½ü12ÍòÃŵÄÉè¼Æ£¬×ã¹»ÑéÖ¤Ò»°ã¹æÄ£µÄÉè¼ÆÁË¡£
¡¾¿ª·¢°åµÄÁÁµã¡¿
1¡¢×î¼ÑµÄÐԼ۱ȡ£ÕâôСµÄ»¨·Ñ£¬¾ÍÄÜÁ¢¿Ì½øÈëCyclone FPGA Óë niosÈíºË´¦ÀíÆ÷µÄÊÀ½ç¡£Ö÷оƬ²ÉÓÃAltera
Cyclone EP1C6Q240C8
£¬°üº¬5980¸öÂß¼µ¥Ôª£¬Ï൱ÓÚ12ÍòÃŵĹæÄ£¡£³¬¹ýFlex10K100£¨4992¸öLCELL£©,¸üÊÇEPM7128£¨128¸öLCELL)µÄ46±¶£¬ÊÛ¼ÛÈ´ÒÀÈ»µÍÁ®¡£
2¡¢Ö§³ÖniosÈíºË´¦ÀíÆ÷¡£ezNiosC6CϵÁÐÊÇĿǰÊÛ¼Û×îµÍ²¢Á¼ºÃÖ§³ÖniosÈíºË´¦ÀíÆ÷µÄFPGA¿ª·¢°å¡£°üº¬64Mbits
DRAM + 16Mbits Flash,×ã¹»ÔËÐдó¶àÊýµÄ³ÌÐò¡£
3¡¢Ö§³ÖUSB¿ÚÈ¡µç¡£½ö½öÐèҪһ̨µçÄÔ£¬¾Í¿ÉÒÔѸËÙ¿ªÊ¼ÄúµÄFPGAÊÔÑ飬²¢²»ÐèÒª¶îÍâµÄµçÔ´¡££¨×¢£ºÇë²Î¿¼µçÄÔÖ÷°åµÄ˵Ã÷Ê飬±£Ö¤USB¿Ú¾ßÓÐÏÞÁ÷±£»¤ÄÜÁ¦£¨¼¸ºõËùÓеÄÖ÷°å¶¼¿ÉÒÔÂú×ãÒªÇ󣩣¬ÒòΪ¿ª·¢°åºÄµç±ä»¯·¶Î§ºÜ´ó£¬ÓÐʱ»á³¬¹ý500mA,ÎÒÃDz»¶ÔÄúʹÓùý³ÌÖÐÔì³ÉµÄUSB¿ÚË𻵸ºÔ𣩡£
4¡¢¿ÉÀ©Õ¹ÐÔÄܺ᣿ª·¢°åÒѾͨ¹ý40PINÅÅÕëÒý³ö54¸öIO£¬·½±ãÄú×Ô¼ºµÄÀ©Õ¹¡£¿ª·¢°å×î´óÖ§³Ö512Mbits
DRAM,64Mbits Flash¡£
¡¾Ïà¹ØÊÔÑé·¶Àý¡¿
1¡¢FPGAʵÑéÒ»_ÊÖ°ÑÊÖ½ÌÄãʵÏÖÁ÷Ë®µÆ
2¡¢FPGAʵÑé¶þ_¿ªÊ¼·ÂÕæ_ÊÖ°ÑÊÖ½ÌÄ㿪ʼRTL·ÂÕæ
3¡¢FPGAʵÑéÈý_ÈçºÎÔËÐкó·ÂÕæ
4¡¢FPGAʵÑéËÄ_ÊÖ°ÑÊÖ½ÌÄãÔËÓÃSignalTapII
5¡¢FPGAʵÑéÎå_ÊÖ°ÑÊÖ½ÌÄãʵÏÖ´®¿ÚͨѶ
6¡¢FPGAʵÑéÁù_ÊÖ°ÑÊÖ½ÌÄãʵÏÖUSB¿ÚͨѶ
7¡¢NiosIIʵÑéÒ»_´´½¨NiosII×îСϵͳ
8¡¢NiosIIʵÑé¶þ-niosIIµÄ·ÂÕæ
9¡¢NiosIIʵÑéÈý-niosIIµÄµ÷ÊÔ
10¡¢NiosIIʵÑéËÄ_´´½¨±ê×¼NiosIIϵͳ
11¡¢NiosIIʵÑéÎå-NiosIIÖÐFlashµÄʹÓÃ
12¡¢NiosIIʵÑéÁù-NiosIIÖÐPWMµÄʹÓÃ
¡¾±¾Õ¾Ô´´FPGA-NIOSIIÏà¹ØÎĵµ¡¿
1¡¢£¨±¾Õ¾Ô´´£©FPGAʵÑéÒ»_ÊÖ°ÑÊÖ½ÌÄãʵÏÖÁ÷Ë®µÆ
2¡¢£¨±¾Õ¾Ô´´£©FPGAʵÑé¶þ_¿ªÊ¼·ÂÕæ_ÊÖ°ÑÊÖ½ÌÄ㿪ʼRTL·ÂÕæ
3¡¢£¨±¾Õ¾Ô´´£©FPGAʵÑéÈý_ÊÖ°ÑÊÖ½ÌÄãÔËÐкó·ÂÕæ
4¡¢£¨±¾Õ¾Ô´´£©FPGAʵÑéËÄ_ÊÖ°ÑÊÖ½ÌÄãÔËÓÃSignalTapII
5¡¢£¨±¾Õ¾Ô´´£©FPGAʵÑéÎå_ÊÖ°ÑÊÖ½ÌÄãʵÏÖ´®¿ÚͨѶ
6¡¢£¨±¾Õ¾Ô´´£©FPGAÊÔÑéÁù_USBͨѶʵÑé
7¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨Ò»£©--NiosÎÞÍ´ÈëÃÅ
8¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨¶þ£©--NIOSIIµÄ·ÂÕæ
9¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨Èý£©--NIOSIIµÄµ÷ÊÔ
10¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨ËÄ£©--StepByStep´´½¨±ê×¼niosIIϵͳ
11¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨Î壩--ÏòNiosϵͳÖÐÌí¼Ó¿Í»§¶¨ÖÆÂß¼
12¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨Áù£©--NiosIIÖÐFlashµÄʹÓÃ
13¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨Æß£©--NIOS´¦ÀíÆ÷ÖÐDRAMµÄʹÓÃ
14¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨°Ë£©--Flash±à³ÌÆ÷µÄʹÓÃ
15¡¢£¨Õ¾³¤Ô´´£©FPGAÒ²·è¿ñ£¨¾Å£©--EDAÈí¼þµÄ°²×°ÓëÅäÖÃ
16¡¢NiosII¿ª·¢³£¼ûÎÊÌâÓë»Ø´ð
17¡¢¹Ü½Å¶ÔÓ¦¹ØÏµ±í
18¡¢ezNiosC6CÓû§ÊÖ²á
19¡¢±¾Õ¾ÊµÑé½Ì³Ì¡¢ÎĵµÔĶÁ˵Ã÷
20¡¢Èí¼þ°²×°ËµÃ÷
¡¾ÆäËû²Î¿¼Îĵµ¡¿££Ñ¡²¿·ÖÁÐÈ¡£¬½ö¹©Ñ§Ï°ÓÃ
1¡¢alteraÈ«¹ú½Ìʦ»áÒéµÄQuartus4.1ʵÑé½²Òå
2¡¢Fpga design flow
3¡¢NiosII_Exercises_Ver3
4¡¢ÓÃSignalTapǶÈëÂß¼·ÖÎöÒÇÑéÖ¤PLDÉè¼Æ
5¡¢AHDLµÄ½éÉÜppt
6¡¢ALTERAµÄ¿ª·¢ppt
7¡¢Altera¿É±à³ÌÓ¦ÓÃ
8¡¢AlteraÆ÷¼þÅäÖÃÊÖ²á
9¡¢cycloneϵÁпª·¢ÊÖ²á
10¡¢Designing_with_Quartus_II_Exercises_Ver10_v4_1
11¡¢quartus2ÖÐÎļòÃ÷ÊÖ²á
12¡¢Quartus IIÖÐÎÄÓû§Ö¸ÄÏ
13¡¢quartusii_handbook
14¡¢FPGA»ù±¾Ê¹ÓÃÎÊÌâfaq
15¡¢nios¿ª·¢Ó¢ÎIJο¼Îĵµ£¨ºÜ¶à£¬²»Ò»Ò»Áо٣©
16¡¢GALʹÓý̳Ì
17¡¢Verilog»ù´¡ÖªÊ¶
18¡¢Verilog HDLÁ·Ï°Ìâ
19¡¢Verilog HDL SYNTHESIS A Practical
Primer
20¡¢testbenchÈëÃÅÎĵµ
21¡¢verilog golden reference
guide
22¡¢verilog_std
23¡¢´úÂë´óÈ«
......
¡¾×°ÏàÇåµ¥¡¿
1¡¢¿ª·¢°å£º1¿é£»
2¡¢ByteBlasterIIÏÂÔØµçÀ£º1Ìõ£»
3¡¢USBÈ¡µçµçÀ£º1Ìõ£»
4¡¢´®¿ÚͨѶµçÀ£¨Á½Í·¿×£©£º1Ìõ£»
5¡¢1ÕÅÓû§¹âÅÌ£¬2ÕÅ×ÊÁϹâÅÌ£¨°üÀ¨QuartusII4.2 + nios2_1_1_b131 + ModelSim6.0
SE + Ïà¹Ø×ÊÁÏ¡¢·¶ÀýµÈ£©
×¢£º
£¨1£©ËùÓÐ1000ÔªÒÔϲúÆ·ÓÉÓÚÀûÈóµ¥±¡£¬×Ô¸¶ÔË·Ñ£¡
ÍâµØ¿Í»§×Ô¸¶ÔË·Ñ20Ôª£¬±¾µØ¿Í»§¹ñ̨×ÔÈ¡¡£
£¨2£©ÎÒÃǵÄÈ«²¿ÍøÕ¾±¨¼Û»òÕßQQ
email±¨¼Û£¬¶¼ÊDz»º¬Æ±µÄ±¨¼Û¡£
±¾¹«Ë¾¿ÉÒÔ¿ªÆÕͨ·¢Æ±£¬µ«ÊÇÈç¹û¿ª·¢Æ±£¬Ò»Âɶà¼Ó5£¥µÄ˰Ǯ¡£»ã¿îʱ£¬ÇëÎñ±Ø×¢Òâ¡£
|